FPGA DSP Firmware Design Engineer
The EW Division of Leidos is looking for a FPGA DSP Firmware Design Engineer to work with a multi-disciplined design team (electrical engineers, systems engineers, scientists, etc) to design, develop, simulate, and integrate challenging DSP FPGA designs and RF sensor systems based on given project requirements. Candidate will have a strong background in Digital Signal Processing (DSP) algorithms and their implementation in MATLAB and FPGAs in support of a fast paced, multi-disciplinary design team. This role will also support integration, test, and verification in the final products.
Analyze, design, simulate, and implement algorithms in hardware descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s).
Collaborate with a multi-disciplined design team (electrical engineers, systems engineers and scientists) to design and integrate challenging DSP FPGA designs and RF sensor systems.
Collaborate with a multi-disciplined design team to design and integrate DSP applications for latest System on a Chip (SoC) implementations such as Xilinx Zynq Ultrascale+, Intel Stratix-10, and Xilinx RFSoC.
Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.
Perform design constraints generation and verification as well as evaluate synthesis and timing performance reports.
Implement and validate signal processing concepts such as FFTs, channelizers, digital filters, digital modulation, digital down/up-conversion, adaptive processing, etc. into either new or existing modular HDL designs.
Analyze, design, simulate, and implement designs which interface to common signaling standards, typical IP hard macros such as SERDES, PLLS, etc. and/or protocols such PCIe, JESD204B, LVDS, etc.
Analyze schematic diagrams for either custom or commercial-off-the shelf (COTS) electronic hardware involving high-speed digital and/or analog circuitry in associated FPGA-centric systems.
Develop and maintain requirements documents, functional specification documents, interface control documents, etc.
Generate and maintain engineering drawings and configuration management policies for FPGA project hierarchy.
Develop project test plans and test procedures, provide test planning support, and assist in the execution of both lab testing and field testing.
Provide occasional technical support and/or field support planning, and other field support in general if needed.
Conduct experimental tests on latest FPGA and SoC evaluation boards, evaluate results, and then develop specifications for selecting next-generation components for deliverable systems.
Work on problems of diverse scope, determining methods and procedures to be used on new assignments, and providing feedback and recommendations to other technical personnel.
Interact with outside customers, suppliers, and functional peer groups.
Some travel and work at remote sites for limited time periods may be occasionally required.
Provide status reports to project managers and/or division production manager as required.
Must have a current Secret clearance with the ability to obtain a TS/SCI level clearance.
Experience with at least one FPGA Integrated Design Environment tool set such as Xilinx Vivado and Mentor Graphics ModelSim.
Experience in signal processing theory and communications systems and the ability to apply theoretical knowledge in resolving real world problems
Experience with MATLAB signal processing environment
BS in Electrical Engineering or Computer Engineering or related degree
Minimum of 4 years of relevant experience
MS in Electrical Engineering or Computer Engineering or related
Experience writing test software in C/C++ or assembly language to validate design
5 to 8 years of relevant experience
Experience with hardware integration, test and debug tools (high-speed logic analyzers, scopes, spectrum analyzers, etc.)
Familiarity with Electronic Warfare applications
Experience with high-speed (> GHz) design techniques
ARM or RISC-V embedded processor based SoC design experience
Experience with performance characteristics of analog data converters, ADCs/DACs.
Familiarity with JESD204B
Existing Top Secret Clearance
Pay Range:Pay Range $81,250.00 - $146,875.00
The Leidos pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.